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M34E02
2 Kbit Serial IC Bus EEPROM Serial Presence Detect for DDR2 DIMMs
FEATURES SUMMARY

Software Data Protection for lower 128 bytes Two Wire I2C Serial Interface 100kHz Transfer Rates 1.7 to 3.6V Single Supply Voltage: BYTE and PAGE WRITE (up to 16 bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Protection More than 1 Million Erase/Write Cycles More than 40 Year Data Retention
Figure 1. Packages
UFDFPN8 (MB) 2x3mm (MLP)
TSSOP8 (DW) 4.4x3mm
November 2004
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M34E02
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TSSOP and MLP Connections (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus . . . . . . . . . . . . . . . . 5 Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6. Result of Setting the Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Setting the Write-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Setting the Write Protection (WC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Write Mode Sequences in a Non Write-Protected Area . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10.Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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M34E02
USE WITHIN A DDR2 DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. DRAM DIMM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Programming the M34E02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DDR2 DIMM Isolated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DDR2 DIMM Inserted in the Application Mother Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Acknowledge when Writing Data or Defining the Write-protection (Instructions with R/W bit=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Acknowledge when Reading the Write Protection (Instructions with R/W bit=1). . . . . . . 13 Figure 11.Serial Presence Detect Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 12.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 14.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 13. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 15.TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 20 Table 14. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 20 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 16. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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M34E02
SUMMARY DESCRIPTION
The M34E02 is a 2 Kbit serial EEPROM memory able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual interline memory modules) with Serial Presence Detect. All the information concerning the DRAM module configuration (such as its access speed, its size, its organization) can be kept write protected in the first half of the memory. This bottom half of the memory area can be writeprotected using two different software write protection mechanisms. By sending the device a specific sequence, the first 128 bytes of the memory become write protected: permanently or resetable. In addition, the device allows the entire memory area to be write protected, using the WC input (for example by tieing this input to VCC). These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 256x8 bits. Figure 2. Logic Diagram
VCC
Note: 1. See the pages after page 19 for package dimensions, and how to identify pin-1.
Device Select Code and RW bit (as described in Table 2), terminated by an acknowledge bit. When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ. Figure 3. TSSOP and MLP Connections (Top View)
M34E02 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI09021
VCC WC SCL SDA
3 E0-E2 SCL WC M34E02 SDA
Table 1. Signal Names
E0, E1, E2 SDA SCL WC Chip Enable Serial Data Serial Clock Write Control Supply Voltage Ground
VSS
AI09020
VCC VSS
I2C uses a two wire serial interface, comprising a bi-directional data line and a clock line. The device carries a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition to access the memory area and a second Device Type Identifier Code (0110) to define the protection. These codes are used together with the voltage level applied on the three chip enable inputs (E2, E1, E0). The device behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a
Power On Reset: VCC Lock-Out Write Protect In order to prevent data corruption and inadvertent Write operations during power up, a Power On Reset (POR) circuit is included. At Power-on, the internal reset is held active until VCC has reached the POR threshold value, and all operations are disabled - the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid VCC (as defined in Table 8) must be applied before applying any logic signal.
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M34E02
SIGNAL DESCRIPTION
Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). Chip Enable (E0, E1, E2) These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. In the end application, E0, E1 and E2 must be directly (not through a pull-up or pull-down resistor) connected to VCC or VSS to establish the Device Select Code. When these inputs are not connected, an internal pull-down circuitry makes (E0,E1,E2) = (0,0,0). The E0 input is used to detect the VHV voltage, when decoding an SWP or CWP instruction. Write Control (WC) This input signal is provided for protecting the contents of the whole memory from inadvertent write operations. Write Control (WC) is used to enable (when driven Low) or disable (when driven High) write instructions to the entire memory area or to the Protection Register. When Write Control (WC) is tied Low or left unconnected, the write protection of the first half of the memory is determined by the status of the Protection Register.
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF)
AI01665
RL
SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS
CBUS 1000
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M34E02
Figure 5. I2C Bus Protocol
SCL
SDA SDA Input SDA Change
START Condition
STOP Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP Condition
AI00792B
Table 2. Device Select Code
Chip Enable Signals Device Type Identifier b7 1 Memory Area Select Code (two arrays) 2 Set Write Protection (SWP) Clear Write Protection (CWP) Permanently Set Write Protection (PSWP) 2 Read SWP Read CWP Read PSWP 2 E2 VSS VSS E2 VSS VSS E2 E1 VSS VCC E1 VSS VCC E1 E0 VHV VHV E0 0 VHV VHV E0 1 1 0 0 0 E2 0 1 E1 1 1 E0 1 1 1 1 b6 0 b5 1 b4 0 Chip Enable Bits b3 E2 0 0 E2 b2 E1 0 1 E1 b1 E0 1 1 E0 RW b0 RW 0 0 0
Note: 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device.
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M34E02
DEVICE OPERATION
The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The memory device is always a slave in all communication. Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Stop Condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. Table 3. Operating Modes
Mode Current Address Read Random Address Read 1 Sequential Read Byte Write Page Write
Note: 1. X = VIH or VIL.
Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low. Memory Addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4bit Device Type Identifier is 1010b; to access the write-protection settings, it is 0110b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode.
RW bit 1 0
WC 1 X X
Bytes 1 1
Initial Sequence START, Device Select, RW = 1 START, Device Select, RW = 0, Address reSTART, Device Select, RW = 1
X X VIL VIL 1 1 16
1 0 0
Similar to Current or Random Address Read START, Device Select, RW = 0 START, Device Select, RW = 0
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M34E02
Figure 6. Result of Setting the Write Protection
FFh Standard Array Memory Area Standard Array 00h Default EEPROM memory area state before write access to the Protect Register 80h 7Fh Standard Array Write Protected Array
FFh
80h 7Fh
00h
State of the EEPROM memory area after write access to the Protect Register
AI01936C
Setting the Write-Protection The M34E02 has a hardware write-protection feature, using the Write Control (WC) signal. This signal can be driven High or Low, and must be held constant for the whole instruction sequence. When Write Control (WC) is held High, the whole memory array (addresses 00h to FFh) is write protected. When Write Control (WC) is held Low, the write protection of the memory array is dependent on whether software write-protection has been set. Software write-protection allows the bottom half of the memory area (addresses 00h to 7Fh) to be write protected irrespective of subsequent states of the Write Control (WC) signal. Software write-protection is handled by three instructions: - SWP: Set Write Protection - CWP: Clear Write Protection - PSWP: Permanently Set Write Protection The level of write-protection (set or cleared) that has been defined using these instructions, remains defined even after a power cycle. Figure 7. Setting the Write Protection (WC = 0)
START
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY ACK CONTROL BYTE
SWP and CWP. If the software write-protection has been set with the SWP instruction, it can be cleared again with a CWP instruction. The two instructions (SWP and CWP) have the same format as a Byte Write instruction, but with a different Device Type Identifier (as shown in Table 2). Like the Byte Write instruction, it is followed by an address byte and a data byte, but in this case the contents are all "Don't Care" (Figure 7). Another difference is that the voltage, VHV, must be applied on the E0 pin, and specific logical levels must be applied on the other two (E1 and E2, as shown in Table 2). PSWP. If the software write-protection has been set with the PSWP instruction, the first 128 bytes of the memory are permanently write-protected. This write-protection cannot be cleared by any instruction, or by power-cycling the device, and regardless the state of Write Control (WC). Also, once the PSWP instruction has been successfully executed, the M34E02 no longer acknowledges any instruction (with a Device Type Identifier of 0110) to access the write-protection settings.
WORD ADDRESS
DATA
ACK
ACK
VALUE VALUE (DON'T CARE) (DON'T CARE)
AI01935B
8/23
STOP
M34E02
Figure 8. Write Mode Sequences in a Non Write-Protected Area
ACK BYTE WRITE START DEV SEL R/W ACK PAGE WRITE START DEV SEL R/W ACK DATA IN N STOP ACK ACK DATA IN 1 ACK DATA IN STOP ACK DATA IN 2 BYTE ADDR
AI01941
ACK
BYTE ADDR
Write Operations Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 8, and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after the Ack bit (in the "10th bit" time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and the device does not respond to any requests. Byte Write After the Device Select Code and the address byte, the bus master sends one data byte. If the addressed location is hardware write-protected, the device replies to the data byte with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device
replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 8. Page Write The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as `rollover' occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If the addressed location is hardware write-protected, the device replies to the data byte with NoAck, and the locations are not modified. After each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition.
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M34E02
Figure 9. Write Cycle Polling Flowchart using ACK
WRITE Cycle in Progress
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by the device
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Address and Receive ACK
STOP
NO
START Condition
YES
DATA for the WRITE Operation
DEVICE SELECT with RW = 1
Continue the WRITE Operation
Continue the Random READ Operation
AI01847C
Minimizing System Delays by Polling On ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 12, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master.
The sequence, as shown in Figure 9, is: - Initial condition: a Write cycle is in progress. - Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). - Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).
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M34E02
Figure 10. Read Mode Sequences
ACK CURRENT ADDRESS READ START DEV SEL R/W NO ACK DATA OUT STOP ACK DEV SEL * START R/W
ACK RANDOM ADDRESS READ START DEV SEL * R/W
ACK
NO ACK DATA OUT STOP NO ACK ACK
AI01942
BYTE ADDR
ACK SEQUENTIAL CURRENT READ START DEV SEL R/W
ACK
ACK
DATA OUT 1
DATA OUT N STOP
ACK SEQUENTIAL RANDOM READ START DEV SEL * R/W
ACK DEV SEL * START
ACK
BYTE ADDR
DATA OUT 1 R/W
ACK
NO ACK
DATA OUT N STOP
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 3rd bytes) must be identical.
Read Operations Read operations are performed independently of whether hardware or software protection has been set. The device has an internal address counter which is incremented each time a byte is read. Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the RW bit set to 1. The device acknowledges this,
and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the RW bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 10, without acknowledging the byte.
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M34E02
Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h. Acknowledge in Read Mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Standby mode. Table 4. DRAM DIMM Connections
DIMM Position 0 1 2 3 4 5 6 7 E2 VSS VSS VSS VSS VCC VCC VCC VCC E1 VSS VSS VCC VCC VSS VSS VCC VCC E0 VSS VCC VSS VCC VSS VCC VSS VCC
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh).
USE WITHIN A DDR2 DIMM
In the application, the M34E02 is soldered directly in the printed circuit module. The three Chip Enable inputs (E0, E1, E2) must be connected to VSS or VCC directly (that is without using a pull-up or pull-down resistor) through the DIMM socket (see Table 4.). The pull-up resistors needed for normal behavior of the I2C bus are connected on the I2C bus of the mother-board (as shown in Figure 11). The Write Control (WC) of the M34E02 can be left unconnected. However, connecting it to VSS is recommended, to maintain full read and write access.
Programming the M34E02 The situations in which the M34E02 is programmed can be considered under two headings: - when the DDR2 DIMM is isolated (not inserted on the PCB motherboard) - when the DDR2 DIMM is inserted on the PCB motherboard DDR2 DIMM Isolated. With specific programming equipment, it is possible to define the M34E02 content, using Byte and Page Write instructions, and its write-protection using the SWP and CWP instructions. To issue the SWP and CWP instructions, the DDR2 DIMM must be inserted in the DDR2-specific slot where the E0 signal can be driven to VHV during the whole instruction. This programming step is mainly intended for use by DDR2 DIMM makers, whose end application manufacturers will want to clear this write-protection with the CWP on their own specific programming equipment, to modify the lower 128 Bytes, and finally to set permanently the write-protection with the PSWP instruction. DDR2 DIMM Inserted in the Application Mother Board. As the final application cannot drive the E0 pin to VHV, the only possible action is to freeze the write-protection with the PSWP instruction. Table 5 and Table 6 show how the Ack bits can be used to identify the write-protection status.
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M34E02
Table 5. Acknowledge when Writing Data or Defining the Write-protection (Instructions with R/W bit=0)
Status WC Input Level Instruction Ack Address Not significant Address Not significant Not significant Not significant Address Not significant Not significant Not significant Address Not significant Address Not significant Address Ack Data Byte Not significant Data Not significant Not significant Not significant Data Not significant Not significant Not significant Data Not significant Data Not significant Data Ack Write Cycle (tW) No No No Yes Yes No No No No No Yes Yes No No
PSWP, SWP or CWP Permanently protected X Page or Byte Write in lower 128 Bytes SWP CWP 0 PSWP Page or Byte Write in lower 128 Bytes SWP 1 CWP PSWP Page or Byte Write 0 PSWP, SWP or CWP Page or Byte Write Not Protected 1 PSWP, SWP or CWP Page or Byte Write
NoAck Ack NoAck Ack Ack Ack NoAck Ack Ack Ack Ack Ack Ack Ack
NoAck Ack NoAck Ack Ack Ack NoAck Ack Ack Ack Ack Ack Ack Ack
NoAck NoAck NoAck Ack Ack NoAck NoAck NoAck NoAck NoAck Ack Ack NoAck NoAck
Protected with SWP
Table 6. Acknowledge when Reading the Write Protection (Instructions with R/W bit=1)
Status Permanently protected Protected with SWP Not Protected Instruction PSWP, SWP or CWP SWP CWP PSWP PSWP, SWP or CWP Ack NoAck NoAck Ack Ack Ack Address Not significant Not significant Not significant Not significant Not significant Ack NoAck NoAck NoAck NoAck NoAck Data byte Not significant Not significant Not significant Not significant Not significant Ack NoAck NoAck NoAck NoAck NoAck
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M34E02
Figure 11. Serial Presence Detect Block Diagram
DIMM Position 7 E2 E1 E0 SCL SDA
R = 4.7k
VCC DIMM Position 6 E2 E1 E0 SCL SDA
VCC DIMM Position 5 E2 E1
VSS
E0
SCL SDA
VCC VSS VCC DIMM Position 4 E2 E1 E0 SCL SDA
VCC DIMM Position 3 E2 E1
VSS
E0
SCL SDA
VSS DIMM Position 2 E2 E1
VCC
E0
SCL SDA
VSS VCC VSS DIMM Position 1 E2 E1 E0 SCL SDA
VSS DIMM Position 0 E2 E1
VCC
E0
SCL SDA
VSS
SCL line
AI01937
SDA line
From the motherboard I2C master controller
Note: 1. E0, E1 and E2 are wired at each DIMM socket in a binary sequence for a maximum of 8 devices. 2. Common clock and common data are shared across all the devices. 3. Pull-up resistors are required on all SDA and SCL bus lines (typically 4.7 k) because these lines are open drain when used as outputs.
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M34E02
MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 7. Absolute Maximum Ratings
Symbol TSTG TLEAD VIO VCC VESD Storage Temperature Lead Temperature during Soldering 1 Input or Output range Supply Voltage Electrostatic Discharge Voltage (Human Body model) 2 E0 Others Parameter Min. -65 Max. 150 Unit C C V V V
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
See note 1 -0.50 -0.50 -0.5 -4000
ECOPACK(R)
10.0 6.5 6.5 4000
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
7191395 specification, and
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M34E02
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the MeasureTable 8. Operating Conditions
Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter Min. 1.7 0 Max. 3.6 70 Unit V C
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 9. AC Measurement Conditions
Symbol CL Load Capacitance Input Rise and Fall Times Input Levels Input and Output Timing Reference Levels Parameter Min. 100 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
Figure 12. AC Measurement I/O Waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
Table 10. Input Parameters
Symbol CIN CIN ZEiL ZEiH ZWCL ZWCH tNS Parameter1,2 Input Capacitance (SDA) Input Capacitance (other pins) Ei (E0, E1, E2) Input Impedance Ei (E0, E1, E2) Input Impedance WC Input Impedance WC Input Impedance Pulse width ignored (Input Filter on SCL and SDA) VIN < 0.3VCC VIN > 0.7VCC VIN < 0.3VCC VIN > 0.7VCC Single glitch 30 800 5 500 100 Test Condition Min. Max. 8 6 Unit pF pF k k k k ns
Note: 1. TA = 25 C, f = 400 kHz 2. Sampled only, not 100% tested.
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M34E02
Table 11. DC Characteristics
Symbol ILI ILO ICC Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current Test Condition (in addition to those in Table 8) VIN = VSS or VCC VOUT = VSS or VCC, SDA in Hi-Z VCC =1.7V, fc=100kHz (rise/fall time < 30ns) VIN = VSS or VCC, VCC = 3.6V Stand-by Supply Current VIN = VSS or VCC, VCC = 1.7V Input Low Voltage (SCL, SDA, WC) Input High Voltage (SCL, SDA, WC) E0 High Voltage Output Low Voltage VHV - VCC 4.8V IOL = 2.1mA, 2.2V VCC 3.6V IOL = 0.7mA, VCC = 1.7V -0.45 0.7VCC 7 0.5 0.3 VCC VCC+1 10 0.4 0.2 A V V V V V Min.1 Max.1 2 2 1 1 Unit A A mA A
ICC1
VIL VIH VHV VOL
Note: 1. Preliminary Data.
Table 12. AC Characteristics
Test conditions specified in Table 9 and 8 Symbol fC tCHCL tCLCH tDL1DL2 2 tDXCX tCLDX tCLQX tCLQV 3 tCHDX 1 tDLCL tCHDH tDHDL tW Alt. fSCL tHIGH tLOW tF tSU:DAT tHD:DAT tDH tAA tSU:STA tHD:STA tSU:STO tBUF tWR Clock Frequency Clock Pulse Width High Clock Pulse Width Low SDA Fall Time Data In Set Up Time Data In Hold Time Data Out Hold Time Clock Low to Next Data Valid (Access Time) Start Condition Set Up Time Start Condition Hold Time Stop Condition Set Up Time Time between Stop Condition and Next Start Condition Write Time 4000 4700 20 250 0 200 200 4700 4000 4000 4700 10 3500 300 Parameter Min. Max. 100 Unit kHz ns ns ns ns ns ns ns ns ns ns ns ms
Note: 1. For a reSTART condition, or following a Write cycle. 2. Sampled only, not 100% tested. 3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
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M34E02
Figure 13. AC Waveforms
tCHCL
tCLCH
SCL tDLCL SDA In tCHDX START Condition SDA Input tCLDX SDA tDXCX Change tCHDH tDHDL START STOP Condition Condition
SCL
SDA In tCHDH STOP Condition tW Write Cycle tCHDX START Condition
SCL tCLQV SDA Out Data Valid tCLQX
AI00795C
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M34E02
PACKAGE MECHANICAL
Figure 14. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Package Outline
D L3
e
b L1
E
E2
L A D2 ddd A1
UFDFPN-01
Note: 1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 13. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm, Package Mechanical Data
millimeters Symbol Typ. A A1 b D D2 ddd E E2 e L L1 L3 N 0.30 8 0.50 0.45 3.00 0.15 - 0.40 0.25 - 0.50 0.15 0.012 8 0.020 0.018 0.25 2.00 1.55 1.65 0.05 0.118 0.006 - 0.016 0.010 - 0.020 0.006 0.55 Min. 0.50 0.00 0.20 Max. 0.60 0.05 0.30 0.010 0.079 0.061 0.065 0.002 Typ. 0.022 Min. 0.020 0.000 0.008 Max. 0.024 0.002 0.012 inches
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M34E02
Figure 15. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
Notes: 1. Drawing is not to scale.
Table 14. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data
millimeters Symbol Typ. A A1 A2 b c CP D e E E1 L L1 N 3.000 0.650 6.400 4.400 0.600 1.000 0 8 8 2.900 - 6.200 4.300 0.450 1.000 0.050 0.800 0.190 0.090 Min. Max. 1.200 0.150 1.050 0.300 0.200 0.100 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295 inches
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M34E02
PART NUMBERING
Table 15. Ordering Information Scheme
Example: Device Type M34 = ASSP I2C serial access EEPROM Device Function E02 = 2 Kbit (256 x 8) SPD (Serial Presence Detect) for DDR2 Operating Voltage F = VCC = 1.7 to 3.6V (100kHz) Package MB = UDFDFPN8 (MLP8) DW = TSSOP8 (4.4x3mm body size) Temperature Range 1 = 0 to 70 C Option blank = Standard Packing T = Tape & Reel Packing Plating Technology blank = Standard SnPb plating P = Lead-Free and RoHS compliant G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free M34E02 - F DW 1 T P
For a list of available options (speed, package, etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Office.
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M34E02
REVISION HISTORY
Table 16. Revision History
Date 13-Nov-2003 01-Dec-2003 Rev. 1.0 1.1 First release TSSOP8 4.4x3 package replaces TSSOP8 3x3 (MSOP8) package. Correction to sentence in "Setting the Write Protection". Correction to specification of tNS values. Always NoACK after Address and Data bytes in Table 6. Improvement in VIO and VCC (min) in Absolute Maximum Ratings table. IOL changed for test condition of VOL. MLP package mechanical data respecified. Soldering temperature information clarified for RoHS compliant devices. First public release Direct connection of E0, E1, E2 to VSS and VCC (see Chip Enable (E0, E1, E2) and USE WITHIN A DDR2 DIMM paragraphs). ZEiL and ZEiH parameters added to Table 10., Input Parameters. E0, E1, E2 removed from the Parameter descriptions of VIL and VIH in Table 11., DC Characteristics. Document status promoted from Product Preview to full Datasheet. Description of Revision
29-Mar-2004
1.2
14-Apr-2004
2.0
24-Nov-2004
3.0
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M34E02
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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